1) Field of the Invention
The present invention relates to a driving apparatus for a display panel having a capacitive load such as an AC driving type plasma display panel (hereinafter referred to as PDP) or an electroluminescence display panel (hereinafter referred to as ELP).
2) Description of the Related Art
Recently, display apparatuses using capacitive light emitting devices such as a PDP or an ELP have been put into practical use as a wall-mounted TV.
FIG. 1 of the accompanying drawings is a diagram showing a schematic structure of the plasma display apparatus using the PDP.
In FIG. 1, a PDP 10 has pairs of row electrodes Y1–Yn and row electrodes X1–Xn in which a row electrode pair corresponding to each row (the first to the n-th rows) of one screen is formed by a pair of row electrodes X and Y. Further, column electrodes Z1–Zm corresponding to the individual columns (the first to the m-th columns) of one screen are formed on the PDP 10 so as to perpendicularly cross the row electrode pairs and to sandwich a dielectric material layer (not shown) and a discharge space (not shown). A discharge cell serving as one pixel is formed in a crossing portion of one pair of row electrodes X and Y, and one column electrode Z.
Each discharge cell has only two states, i.e., “light emmission” and “non-light emmisssion”, depending on whether a discharge occurs in the discharge cell or not. That is to say, the discharge cell expresses only two gradating luminances, i.e., the lowest luminance (non-light emitting state) and the highest luminance (light emitting state).
A driving apparatus 100 is thus utilized to execute a gradation driving using a subfield method in order to obtain the halftone luminance corresponding to a video signal supplied to the PDP 10 having the light emitting devices, i.e., the discharge cells.
According to the subfield method, the supplied video signal is converted into pixel data of N bits corresponding to each pixel, and a display period of one field is divided into N subfields in correspondence with each bit digit of those N bits. The number of times of discharge corresponding to a weight of the subfield is allocated to each subfield. The discharge is selectively caused only in the subfield based on the video signal. The halftone luminance corresponding to the video signal is obtained by the total number of times of the discharge caused (in one field display period) in each subfield.
A selective erasure address method is known as a method to gradation-drive the PDP with the subfield method.
FIG. 2 of the accompanying drawings is a diagram showing application timing of various drive pulses to be applied by the driving apparatus 100 to the column electrodes and row electrodes of the PDP 10 in one subfield when the gradation-driving is executed based on the selective erasure address method.
First, the driving apparatus 100 simultaneously applies reset pulses RPX of negative polarity to the row electrodes X1–Xn, and, reset pulses RPY of positive polarity to the row electrodes Y1–Yn (all-resetting step Rc).
All discharge cells in the PDP 10 are reset-discharged in response to the applying of the reset pulses RPX and RPY and wall charges of a predetermined amount are uniformly formed in each discharge cell. All of the discharge cells are, thus, initialized to “light emitting cells”.
The driving apparatus 100 converts the supplied video signal into cell data of, for example, 8 bits per each pixel (cell). The driving apparatus 100 obtains cell data bits by dividing the cell data according to each bit digit and generates a driving pulse having a pulse voltage corresponding to a logic level of the cell data bit. For example, the driving apparatus 100 generates a cell data pulse DP of a high voltage when the cell data bit is set to logic level “1” and of a low voltage (0 volt) when the cell data bit is set to logic level “0”. The driving apparatus 100 applies the cell data pulse groups DP11−1m, DP21-2m, DP31-3m, . . . and DPn1-nm, which are formed by grouping the cell data pulses in each row (m pulses) for all the cell data pulses DP11–DPnm in one screen (n rows×m columns), to the column electrodes Z1–Zm one by one as shown in FIG. 2. In each application timing of the cell data pulse group DP, the driving apparatus 100 further generates a scan pulse SP as shown in FIG. 2, which is sequentially applied to the row electrodes Y1–Yn (cell data writing step Wc). In this instance, a discharge (selective erasure discharge) occurs only in the discharge cells in crossing portions of the “rows” to which the scan pulses SP have been applied and the “columns” to which the high voltage cell data pulses DP have been applied, and the wall charges remaining in those discharge cells are selectively erased. The discharge cells initialized to the status of “light emitting cells” in the all-resetting step Rc are, consequently, shifted to “non-light emitting cells”. The selective erasure discharge as mentioned above does not occur in the discharge cells formed in crossing portions of the “rows” and the “columns” to which the cell data pulses DP of the low voltage have been applied, even though the scan pulses SP have been applied to the “rows” of the discharge cells. Thus the status initialized in the all-resetting step Rc, namely, the status of “light emitting cell” is maintained.
The driving apparatus 100 applies sustain pulses IPX of positive polarity repetitively to the row electrodes X1–Xn as shown in FIG. 2, and the driving apparatus applies a sustain pulse IPY of positive polarity repetitively to the row electrodes Y1–Yn as shown in FIG. 2 during a period when no sustain pulse IPX is applied to the row electrodes X1–Xn (light emission sustaining step Ic).
In this instance, only the discharge cells in which the wall charges remain, namely, only the “light emitting cells” discharge (sustain-discharge) every time the sustain pulses IPX and IPY are alternately applied. That is, only the discharge cells set as “light emitting cells” in the cell data writing step Wc repeat the light emission due to the sustain-discharge only the number of times corresponding to the weight of this subfield and sustain the light emitting state. The number of applying times of the sustain pulses IPX and IPY has been previously setup in accordance with the weight of each subfield.
The driving apparatus 100 applies erasing pulses EP to the row electrodes X1–Xn as shown in FIG. 2 (erasing step E). All of the discharge cells are, thus, allowed to erasure-discharge at once, thereby extinguishing the wall charges remaining in each discharge cell.
By executing the series of operations as mentioned above a plurality of times in one field, the halftone luminance corresponding to the video signal can be derived.
However, when the cell data pulse is applied to the column electrodes of the capacitive display panel such as a PDP and an ELP, the charge or discharge is necessary for every row in writing data even on the row electrodes where no data is written. Furthermore, the charge or discharge is caused in the capacitance existing between the adjacent column electrodes. Therefore there is a problem that a large amount of electric power is consumed in writing the cell data.